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never stop thinking. hyb25d128400at(l)-[6/7/8] hyb25d128800at(l)-[6/7/8] hyb25d128160at(l)-[6/7/8] 128 mbit double data rate sdram ddr sdram data sheet, rev. 1.06, jan. 2003 memory products
edition 2004-01 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hyb25d128400at(l)-[6/7/8] hyb25d128800at(l)-[6/7/8] hyb25d128160at(l)-[6/7/8] 128 mbit double data rate sdram ddr sdram data sheet, rev. 1.06, jan. 2003 memory products
template: mp_a4_v2.2_2003-10-07.fm hyb25d128400at(l)-[6/7/8], hyb25d128800at(l)-[6/7/8], hyb25d128160at(l)-[6/7/8] revision history: rev. 1.06 2004-01 previous version: rev 1.05 2002-11 rev 1.06 page subjects (major changes since last revision) all editorial changes we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram data sheet 5 rev. 1.06, 2004-01 09192003-lfq1-r60g 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.3 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.4 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 dll enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.2 output drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.1 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.2 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.3 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.4 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.5 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.6 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 normal strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3 weak strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.1 i dd current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table of contents
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram overview data sheet 6 rev. 1.06, 2004-01 09192003-lfq1-r60g 1overview 1.1 features ? double data rate architecture: two data transfers per clock cycle bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver dqs is edge-aligned with data for reads and is center-aligned with data for writes differential clock inputs (ck and ck ) four internal banks for concurrent operation data mask (dm) for write data. the x16 organization has two (ldm, udm), one per byte. dll aligns dq and dqs transitions with ck transitions commands entered on each positive ck edge; data and data mask referenced to both edges of dqs burst lengths: 2, 4, or 8 cas latency: 2, 2.5, (3) auto precharge option for each burst access auto refresh and self refresh modes 15.6 s maximum average periodic refresh interval (4k refresh) 2.5v (sstl_2 compatible) i/o v ddq =2.5v 0.2 v / v dd =2.5v 0.2v tsop66 package table 1 performance 1.2 description the 128mb ddr sdram is a high-speed cmos, dynami c random-access memory containing 1,073,741,824 bits. it is internally configured as a quad-bank dram. the 128mb ddr sdram uses a double-data-rate architectu re to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 128mb ddr sdram effect ively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half- clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by th e ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 128mb ddr sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered part number speed code ? 6?7 ? 8unit speed grade component ddr333b ddr266a ddr200 ? module pc2700?2533 pc2100-2033 pc1600-2022 ? max. clock frequency @cl3 f ck3 166 ? ? mhz @cl2.5 f ck2.5 166 143 125 mhz @cl2 f ck2 133 133 100 mhz
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram overview data sheet 7 rev. 1.06, 2004-01 09192003-lfq1-r60g coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipelined, multibank archit ecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all inputs are compatible with the jedec standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. table 2 ordering information 1) 1) low power versions have a ?l? in the partnumber, for example hyb25d128400atl-8. these components are specifically selected for low idd6 self refresh currents. type cas latency clock (mhz) cas latency clock (mhz) speed org. package hyb25d128400at(l)-8 2.5 125 2 100 ddr200 4 66 pin tsop-ii hyb25d128800at(l)-8 8 hyb25d128160at(l)-8 16 hyb25d128400at(l)-7 143 133 ddr266a 4 hyb25d128800at(l)-7 8 hyb25d128160at(l)-7 16 hyb25d128400at(l)-6 166 133 ddr333 4 hyb25d128800at(l)-6 8 hyb25d128160at(l)-6 16
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram pin configuration data sheet 8 rev. 1.06, 2004-01 09192003-lfq1-r60g 2 pin configuration figure 1 pin configuration 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc nc nc dq2 v ddq nc nc v dd nc nc we cas ras cs nc ba0 ba1 v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc nc nc dq5 v ssq dqs nc v ref v ss dm ck ck cke nc nc a11 a9 v dd nc v ddq nc dq0 v ssq v ddq nc dq1 v ssq nc nc nc nc v ddq nc nc v dd nc nc we cas ras cs nc ba0 ba1 v ss nc v ssq nc dq3 v ddq v ssq nc dq2 v ddq nc nc nc nc v ssq dqs nc v ref v ss dm ck ck cke nc nc a11 a9 a10/ap a0 a1 a2 a3 v dd a10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss a8 a7 a6 a5 a4 v ss 32mb x 4 16mb x 8 v dd dq0 v ddq dq1 dq2 v ssq v ddq dq5 dq6 v ssq dq7 nc dq3 dq4 v ddq ldqs nc v dd nc ldm we cas ras cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd 8mb x 16 v ss dq15 v ssq dq14 dq13 v ddq v ssq dq10 dq9 v ddq dq8 nc dq12 dq11 v ssq udqs nc v ref v ss udm ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 v ss
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram pin configuration data sheet 9 rev. 1.06, 2004-01 09192003-lfq1-r60g table 3 pin definitions and functions symbol type function ck, ck clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of th e positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and outp ut drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power-down. input buffers, excluding cke, are disabled during self refresh. cs chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. ras , cas , we command inputs: ras , cas and we (along with cs ) define the command being entered. dm udm, ldm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. for the 16, ldm corresponds to the data on dq0-dq7; udm corresponds to the data on dq8-dq15. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 - a11 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. dq input data input/output: data bus. dqs udqs,ldqs input data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. used to capture write data.for the 16, ldqs corresponds to the data on dq0-dq7; udqs corresponds to the data on dq8- dq15. nc input no connect: no internal electrical connection is present. v ddq input dq power supply: 2.5v 0.2v. v ssq input/out- put dq ground v dd input/out- put power supply: 2.5v 0.2v. v ss ground v ddq v ref supply sstl_2 reference voltage: ( v ddq / 2)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram pin configuration data sheet 10 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 2 block diagram (32mb 4) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 11 command decode a0-a11, ba0, ba1 cke 12 14 i/o gating dm mask logic bank0 memory array (4096 x 1024 x 8) sense amplifiers bank1 bank2 bank3 12 10 1 2 2 refresh counter 4 4 4 input register 1 1 1 1 1 8 8 2 8 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 4 4 4 4 4 8 dq0-dq3, dm dqs 1 read latch write fifo & drivers note: this functional block diagram is inten ded to facilitate user understanding of the operation of the device; it does not repr esent an actual circuit implementation. note: dm is a unidirectional signal (input only ), but is internally loaded to match the load of the bidirectional dq and dqs signals. column decoder 1024 (x8) row-address mux registers 12 8192 bank0 row-address latch & decoder 4096 address register drivers bank control logic 14 ck
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram pin configuration data sheet 11 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 3 block diagram (16mb 8) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 10 command decode a0-a11, ba0, ba1 cke 14 14 i/o gating dm mask logic bank0 memory array (4096 x 512 x 16) sense amplifiers bank1 bank2 bank3 12 9 1 2 2 refresh counter 8 8 8 input register 1 1 1 1 1 16 16 2 16 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 8 8 8 8 8 16 dq0-dq7, dm dqs 1 read latch write fifo & drivers note: this functional block diagram is intende d to facilitate user understanding of the operation of the device; it does not re present an actual ci rcuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional dq and dqs signals. column decoder 512 (x16) row-address mux registers 12 8192 bank0 row-address latch & decoder 4096 address register drivers bank control logic 12 ck
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram pin configuration data sheet 12 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 4 block diagram (8mb 16) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 9 command decode a0-a11, ba0, ba1 cke 14 14 i/o gating dm mask logic bank0 memory array (4096 x 256x 32) sense amplifiers bank1 bank2 bank3 12 8 1 2 2 refresh counter 16 16 16 input register 1 1 1 1 1 32 32 2 32 clk out data mask data ck, col0 col0 col0 clk in mux dqs generator 16 16 16 16 16 32 dq0-dq15, dm ldqs, udqs 2 read latch write fifo & drivers note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: udm and ldm are unidirectional signals (input only), but is internally loaded to match the load of the bidirectional dq , udqs and ldqs signals. column decoder 256 (x32) row-address mux registers 12 8192 bank0 row-address latch & decoder 4096 address register drivers bank control logic 12 ck
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 13 rev. 1.06, 2004-01 09192003-lfq1-r60g 3 functional description the 128mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 134,217,728 bits. the 128mb ddr sdram is internally configured as a quad-bank dram. the 128mb ddr sdram uses a double-data-rate architecture to achieve high-speed operation. the double-data- rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 128mb ddr sdram consists of a single 2n -bit wide, one clock cycle data transfer at the internal dra m core and two corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a11 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the followin g sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device operation. 3.1 initialization ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following criteria must be met: no power sequencing is specified during power up or power down given the following criteria: v dd and v ddq are driven from a single power converter output v tt meets the specification a minimum resistance of 42 ohms limits the input current from the v tt supply into any pin and v ref tracks v ddq /2 or the following relationsh ip must be followed: v ddq is driven after or with v dd such that v ddq < v dd + 0.3 v v tt is driven after or with v ddq such that v tt < v ddq + 0.3v v ref is driven after or with v ddq such that v ref < v ddq + 0.3v the dq and dqs outputs are in the high-z state, where they remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a mode register set command should be issued for the extended mode register, to enable the dll, then a mode register set command should be issued for the mode register, to reset the dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any executable command. during the 200 cycles of clock for dll locking, a de select or nop command must be app lied. after the 200 clock cycles, a precharge all command should be applied, placing the device in the ?all banks idle? state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated (i.e. to program operating parameters without resetting the dll) must be perform ed. following these cycles, the ddr sd ram is ready for normal operation. 3.2 mode register definition the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). mode register bits a0-a2 specify the burst length, a3 spec ifies the type of burst (sequential or interleaved), a4- a6 specify the cas latency, and a7-a11 specify the operating mode.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 14 rev. 1.06, 2004-01 09192003-lfq1-r60g the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements results in unspecified operation. 3.2.1 burst length read and write accesses to the ddr s dram are burst oriented, with the bu rst length being pr ogrammable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. mr mode register definition (ba[1:0] = 00 b ) ba1 ba0 a12 a13 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 mode cl bt bl reg. addr w w w w field bits type description bl [2:0] w burst length number of sequential bits per dq related to one read/write command; see chapter 3.2.1 . note: all other bit comb inations are reserved. 000 001 2 010 4 011 8 100 101 110 111 bt 3w burst type see table 4 for internal address sequence of low order address bits; see chapter 3.2.2 . 0 sequential 1 interleaved cl [6:4] w cas latency number of full clocks from read command to first data valid window; see chapter 3.2.3 . note: all other bit comb inations are reserved. 000 001 010 2 011 (3.0 optional, not covered by this data sheet) 100 101 110 1.5 for ddr200 components only 101 2.5 mode [13:7] w operating mode 000 valid normal oper ation without dll reset 010 valid normal oper ation without dll reset 001 test mode see chapter 3.2.4 . note: all other bit comb inations are reserved.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 15 rev. 1.06, 2004-01 09192003-lfq1-r60g when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when th e burst length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. 3.2.2 burst type accesses within a given burst may be programmed to be eith er sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 4 . notes: 1. for a burst length of two, a1-ai selects the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached with in a given sequence above, the following access wraps within the block. 3.2.3 read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 2, 2.5 or 3 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operati on or incompatibility with futu re versions may result. table 4 burst definition burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 200-10-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0000-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0011-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0102-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0113-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1004-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1015-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1106-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1117-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 16 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.2.4 operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a11 set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-a11 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. a mode register set command issued to reset the dll should always be followed by a mode register set command to select normal operating mode. all other combinations of values for a7-a11 are reserved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or incompatibility wit h future versio ns may result. figure 5 required cas latencies nop nop nop nop nop read cas latency = 2, bl = 4 shown with nominal t ac , t dqsck , and t dqsq . ck ck command dqs dq don?t care cl=2 nop nop nop nop nop read cas latency = 2.5, bl = 4 ck ck command dqs dq cl=2.5
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 17 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.3 extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions include dll enable/disable, and output drive strength selection (optional). these functions are controlled via the bits shown in the extended mode register definiti on. the extended mode register is programmed via the mode register set command (with ba0 = 1 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements result in unspecified operation. 3.3.1 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must oc cur before a read command can be issued. this is the reason 200 clock cycles must occur before issuing a read or write command upon exit of self refresh operation. 3.3.2 output dr ive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. i-v curves for the normal drive strength are included in this document. in addition this design ve rsion supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during mode register set. i-v curves for the weak dr iver mode will be included in this document later. emr extended mode register definition (ba[1:0] = 01 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 0 1 operating mode ds dll reg. addr w w w field bits type description dll 0w dll status see chapter 3.3.1 . 0 enabled 1 disabled ds 1w drive strength see chapter 3.3.2 , chapter 4.2 and chapter 4.3 . 0normal 1weak mode [12:2] w operating mode note: all other bit combinations are reserved. 0 normal operation
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 18 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.4 commands deselect the deselect function prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to a ddr sdram. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a0-a11, ba0 an d ba1. see mode register descriptions in the register definition section. the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a11 selects the row. this row remains active (or open) for accesses until a precharge (or read or write with auto precharge) is issued to that bank. a precharge (or read or write with auto precharge) command must be issued and completed before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 8, j = don?t care] for 16, [i = 9, j = don?t care] for 8 and [i = 9, j = 11] for 4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. write the write command is used to initiate a burst write access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 9, j = don?t care] for 8; where [i = 9, j = 11] for 4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data is written to memory; if the dm signal is registered high, the corresponding data inputs are ignored, and a write is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same in dividual-bank precharge functions described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of th e bank/row that is addressed with the read or write
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 19 rev. 1.06, 2004-01 09192003-lfq1-r60g command is automatically performed upon completion of th e read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each indi vidual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge ( t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most re-cently registered read command prior to the burst terminate co mmand is truncated, as shown in the operation section of this data sheet. auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas before ras (cbr) refresh in previous dram types. this command is nonpersi stent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 128mb ddr sdram requires auto refresh cycles at an average periodic interval of 15.6 s (maximum). to allow for improv ed efficiency in scheduling and switching betwe en tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted in the system, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 15.6 s. this maximum absolute interval is short enough to allow for dll updates intern al to the ddr sdram to be restricted to auto refresh cycles, without allowing too much drift in t ac between updates. self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated as an auto refresh command coincident with cke transitioning low. the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except cke (low) are ?don?t care? during self refresh operation. the procedure for exiting self refresh requires a sequence of commands. ck (and ck ) must be stable prior to cke returning high. once cke is high, the sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other command.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 20 rev. 1.06, 2004-01 09192003-lfq1-r60g table 5 truth table 1a: commands name (function) cs ras cas we address mne notes deselect (nop) h x x x x nop 1)2) no operation (nop) l h h h x nop 1)2) active (select bank and activate row) l l h h bank/row act 1)3) read (select bank and column, and start read burst) l h l h bank/col read 1)4) write (select bank and column, and start write burst) l h l l bank/col write 1)4) burst terminate l h h l x bst 1)5) precharge (deactivate row in bank or banks) l l h l code pre 1)6) auto refresh or self refresh (enter self refresh mode) l l l h x ar/ sr 1)7)8) mode register set l l l l op-code mrs 1)9) 1) cke is high for all commands shown except self refresh. 2) ba0, ba1 select either the base or the extended mode regi ster (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; ot her combinations of ba0-ba1 are rese rved; a0-a12 provide the op-code to be written to the selected mode register). 3) ba0-ba1provide bank address and a0-a12 provide row address. 4) ba0, ba1 provide bank address; a0-ai provide column address (where i = 8 for 16, i = 9 for 8 and 9, 11 for 4); a10 high enables the auto precharge fe ature (nonpersistent), a10 low disa bles the auto precharge feature. 5) internal refresh counter controls row and bank addressi ng; all inputs and i/os are ?don?t care? except for cke. 6) applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts. 7) a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks ar e precharged and ba0, ba1 are ?don?t care?. 8) this command is auto refresh if cke is high; self refresh if cke is low. 9) deselect and nop are functionally interchangeable. table 6 truth table 1b: dm operation name (function) dm dqs notes write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit hx 1)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 21 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.5 operations 3.5.1 bank/row activation before any read or write commands can be issued to a bank within the ddr sdram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0-a11, ba0 and ba1 (see activating a specific row in a specific bank), which dec ode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (pre charged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which resu lts in a reduction of total row-access overhead. the minimum time interval between successive acti ve commands to different banks is defined by t rrd . figure 6 activating a specific row in a specific bank figure 7 t rcd and t rrd definition ra ba high ra = row address. ba = bank address. ck ck cke cs ras cas we a0-a11 ba0, ba1 don?t care row act nop col row ba y ba y ba x act nop nop ck ck command a0-a11 ba0, ba1 don?t care rd/wr t rcd t rrd rd/wr nop nop
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 22 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.5.2 reads subsequent to programming the mode register with cas latency, burst type, and burst length, read bursts are initiated with a read command, as shown on figure 8 "read command" on page 22 . the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precha rge is enabled, the row that is accessed starts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustration s, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address is available following the cas latency after the read command. each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of ck and ck ). figure 9 "read burst: cas latencies (burst length = 4)" on page 23 shows general timing for each supported cas latency setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. upon completion of a burst, assuming no other commands have been initiated, the dqs goes hig h-z. data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued cycles after the first read command, where equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). this is shown on figure 10 "consecutive read bursts: cas latencies (burst length = 4 or 8)" on page 24 . a read command can be initiated on any clock cycle following a previous read command. nonconsecutive read data is illustrated on figure 11 "non-consecutive read bursts: cas latencies (burst length = 4)" on page 25 . full-speed figure 12 "random read accesses: cas latencies (burst length = 2, 4 or 8)" on page 26 within a page (or pages) can be performed as shown on page 23 . figure 8 read command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca x4: a0-a9, a11 x8: a0-a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck x16: a0-a8
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 23 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 9 read burst: cas latencies (burst length = 4) cas latency = 2 nop nop nop nop nop read ck ck command address dqs dq cas latency = 2.5 don?t care ba a,col n doa-n cl=2.5 nop nop nop nop nop read ck ck command address dqs dq ba a,col n doa-n do a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . cl=2
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 24 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 10 consecutive read bursts: cas latencies (burst length = 4 or 8) cas latency = 2 nop read nop nop nop read ck ck command address dqs dq cl=2 baa, col n baa, col b don?t care do a-n (or a-b) = data out from bank a, column n (or bank a, column b). when burst length = 4, the bursts are concatenated. when burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following do a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following do a-b. shown with nominal t ac , t dqsck , and t dqsq . cas latency = 2.5 nop read nop nop nop read ck ck command address dqs dq cl=2.5 baa, col n baa,col b doa-n doa- n doa- b doa-b
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 25 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 11 non-consecutive read bursts: cas latencies (burst length = 4) cas latency = 2 nop nop read nop nop read ck ck command address dqs dq do a-n doa- b do a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programm ed order following do a-n (and following do a-b). shown with nominal t ac , t dqsck , and t dqsq . don?t care baa, col n baa, col b cl=2 cas latency = 2.5 nop nop read nop nop read do a-n doa- b baa, col n baa, col b cl=2.5 ck ck command address dqs dq nop
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 26 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 12 random read accesses: cas latencies (burst length = 2, 4 or 8) data from any read burst may be truncated with a burst terminate command, as shown on figure 9 "read burst: cas latencies (burst length = 4)" on page 23 . the burst terminate latency is equal to the read (cas) latency, i.e. the burst terminate command should be issued cycles after the read command, where equals the number of desired data element pairs. data from any read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown on figure 14 "read to write: cas latencies (burst length = 4 or 8)" on page 28 . the example is shown for t dqss (min). the t dqss (max) case, not shown here, has a longer bus idle time. t dqss (min) and t dqss (max) are defined in the section on writes. a read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated). the precharge command should be issued cycles after the read command, where equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). this is shown on figure 15 "read to precharge: cas latencies (burst length = 4 or 8)" on page 29 for read latencies of 2 and 2.5. following the precharge command, a subsequent command to the same bank cannot be doa-n cas latency = 2 read read read nop nop read doa-b doa-n' doa-x doa-x' doa-b? doa-g ck ck command address dqs dq do a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address lsb inverted). reads are to active rows in any banks. shown with nominal t ac , t dqsck , and t dqsq . don?t care baa, col n baa, col x baa, col b baa, col g cl=2 doa-n cas latency = 2.5 read read read nop nop read doa-b doa-n' doa-x doa-x' doa-b? ck ck command address dqs dq baa, col n baa, col x baa, col b baa, col g cl=2.5
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 27 rev. 1.06, 2004-01 09192003-lfq1-r60g issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that woul d result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 13 terminating a read burst: cas latencies (burst length = 8) cas latency = 2 nop bst nop nop nop read ck command address dqs dq do a-n = data out from bank a, column n. cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . doa-n don?t care ck baa, col n cl=2 cas latency = 2.5 nop bst nop nop nop read ck command address dqs dq doa-n ck baa, col n cl=2.5 no further output data after this point. dqs tristated. no further output data after this point. dqs tristated.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 28 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 14 read to write: cas latencies (burst length = 4 or 8) cas latency = 2 bst nop write nop nop read di a-b ck ck command address dqs dq dm doa-n do a-n = data out from bank a, column n 1 subsequent elements of data out appear in the programmed order following do a-n. data in elements are applied following dl a-b in the programmed order, according to burst length. don?t care baa, col n baa, col b cl=2 t dqss (min) cas latency = 2.5 bst nop nop write nop read ck ck command address dqs dq dm doa-n baa, col n baa, col b cl=2.5 t dqss (min) dla-b shown with nominal t ac , t dqsck , and t dqsq . . di a-b = data in to bank a, column b
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 29 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 15 read to precharge: cas latencies (burst length = 4 or 8) cas latency = 2 nop pre nop nop act read ck ck command address dqs dq doa-n do a-n = data out from bank a, column n. cases shown are either uninterrupted bur sts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . don?t care ba a, col n ba a or all ba a, row cl=2.5 cas latency = 2.5 nop pre nop nop act read ck ck command address dqs dq doa-n t rp ba a, col n ba a or all ba a, row cl=2 t rp
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 30 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.5.3 writes write bursts are initiated with a write command, as shown on figure 16 "write command" on page 31 . the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the gener ic write commands used in the follo wing illustrations, auto precharge is disabled. during write bursts, the first valid data-in element is registered on the first rising edge of dqs following the write command, and subsequent data elements are registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first corresponding rising edge of dqs ( t dqss ) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the write diagrams that follow are drawn for the two extreme cases (i.e. t dqss (min) and t dqss (max)). figure 17 "write burst (burst length = 4)" on page 32 shows the two extremes of t dqss for a burst of four. upon completion of a burst, assuming no other commands have been initiated, the dqs enters high-z and any additional input data is ignored. data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. th e new write command can be issued on any positive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued cycles after the first write command, where equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). figure 18 "write to write (burst length = 4)" on page 33 shows concatenated bursts of 4. an exam ple of non-consecutiv e writes is shown o n figure 19 "write to write: max. dqss, non-consecutive (burst length = 4)" on page 34 . full-speed random write accesses within a page or pages can be performed as shown on figure 20 "random write cycles (burst length = 2, 4 or 8)" on page 35 . data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr (write to read) should be met as shown on figure 21 "write to read: non-interrupting (cas latency = 2; burst length = 4)" on page 36 . data for any write burst may be truncated by a subsequent read command, as shown in the figures on figure 22 "write to read: interrupting (cas latency = 2; burst length = 8)" on page 37 to figure 24 "write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8)" on page 39 . note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in must be masked with dm, as shown in the diagrams noted previously. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met as shown on figure 25 "write to precharge: non-interrupting (burst length = 4)" on page 40 . data for any write burst may be truncated by a subs equent precharge command, as shown in the figures on figure 26 "write to precharge: interrupting (burst length = 4 or 8)" on page 41 to figure 24 "write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8)" on page 39 . note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data in should be masked with dm. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a write burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same op eration that would result from the same burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 31 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 16 write command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca x4: a0-a9, a11 x8: a0-a9 x16: a0-a8 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 32 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 17 write burst (burst length = 4) t1 t2 t3 t4 t dqss (max) nop nop nop write di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. a10 is low with the write comm and (auto precharge is disabled). ck ck command address dqs dq dm don?t care maximum dqss ba a, col b t1 t2 t3 t4 t dqss (min) nop nop nop write ck ck command address dqs minimum dqss ba a, col b dq dm dla-b dla-b
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 33 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 18 write to write (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss nop write nop nop nop write di a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don?t care t1 t2 t3 t4 t5 t6 minimum dqss nop write nop nop nop write ck ck command address dqs dq dm baa, col b baa, col n ba, col b ba, col n t dqss (min) di a-b di a-n di a-b di a-n
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 34 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 19 write to write: max. dqss, non-consecutive (burst length = 4) t1 t2 t3 t4 t5 t dqss (max) nop nop write nop write di a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don?t care baa, col b baa, col n di a-b di a-n
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 35 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 20 random write cycles (burst length = 2, 4 or 8) t1 t2 t3 t4 t5 t dqss (max) maximum dqss write write write write write di a-b di a-n di a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address lsb inverted). each write command may be to any bank. di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm don?t care baa, col b baa, col x baa, col n baa, col a baa, col g t1 t2 t3 t4 t5 minimum dqss write write write write write di a-b di a-n di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm baa, col b baa, col x baa, col n baa, col a baa, col g t dqss (min) di a-g
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 36 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 21 write to read: non-interrupting (cas latency = 2; burst length = 4) cl = 2 t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write di a-b nop di a-b = data in for bank a, column b. 3 subsequent elements of data in are appli ed in the programmed order following di a-b. a non-interrupted burst is shown. t wtr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write comm and (auto precharge is disabled). the read and write commands may be to any bank. ck ck command address dqs dq dm don?t care maximum dqss baa, col b baa, col n t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write nop ck ck command address minimum dqss baa, col b baa, col n t dqss (max) di a-b dqs dq dm t dqss (min) cl = 2
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 37 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 22 write to read: interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positiv e ck edge after the last data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). the read and write commands are not necessarily to the same bank. dia- b ck ck command address dqs dq dm don?t care baa, col b baa, col n t wtr cl = 2 t1 t2 t3 t4 t5 t6 minimum dqss nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq dm cl = 2 t dqss (min) 1 = these bits are incorrectly written into the memory array if dm is low. 11 11
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 38 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 23 write to read: minimum dqss, odd number of data (3-bit write), interrupting (cas latency = 2; burst length = 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair (not the last desired data in element) the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). the read and write commands are not necessarily to the same bank. don?t care t1 t2 t3 t4 t5 t6 nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq cl = 2 t dqss (min) dm 122 1 = this bit is correctly written in to the memory array if dm is low. 2 = these bits are incorrectly written into the memory array if dm is low.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 39 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 24 write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (nom) nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). the read and write commands are not necessarily to the same bank. di a-b ck ck command address dqs dq dm don?t care baa, col b baa, col n t wtr cl = 2 1 = these bits are incorrectly written into the memory array if dm is low. 1 1
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 40 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 25 write to precharge: non-interrupting (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) nop nop nop nop write di a-b pre di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wr is referenced from the first positiv e ck edge after the last data in pair. a10 is low with the write comm and (auto precharge is disabled). ck ck command address dqs dq dm don?t care ba a, col b ba (a or all) t wr maximum dqss t1 t2 t3 t4 t5 t6 nop nop nop nop write pre ck ck command address ba a, col b ba (a or all) t wr minimum dqss di a-b dqs dq dm t dqss (min) t rp t rp
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 41 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 26 write to precharge: interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst, for burst length = 8. a10 is low with the write comm and (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dq s becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address maximum dqss di a-b 11 2 dqs dq dm t dqss (max) t rp t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) minimum dqss t wr t rp di a-b 11 dqs dq dm t dqss (min) 2 ba a, col b ba (a or all) t wr 3 = these bits are incorrectly written into the memory array if dm is low. 3 3 3 3
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 42 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 27 write to precharge: minimum dqss, odd numb er of data (1-bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 1 data element is written. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t wr t rp di a-b dqs dq t dqss (min) 2 11 dm 344 3 = this bit is correctly written into the memory array if dm is low. 4 = these bits are incorrectly written into the memory array if dm is low.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 43 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 28 write to precharge: nominal dqss (2-bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the fi rst positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t rp t dqss (nom) di a-b 1 2 dqs dq dm 1 t wr 3 3 3 = these bits are incorrectly written into the memory array if dm is low.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 44 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.5.4 precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. figure 29 precharge command ba high ba = bank address ck ck cke cs ras cas we a10 ba0, ba1 don?t care all banks one bank (if a10 is low, otherwise don?t care). a0-a9, a11
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 45 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.5.5 power-down power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as ac tive power-down. entering power-down deactivates the input and output buffers, excluding ck, ck and cke. the dll is still running in power down mode, so for maximum power savings, the user has the option of disabling the dll prior to entering power-down. in that case, the dll must be enabled afte r exiting power-down, and 200 clock cycles must occur before a read command can be issued. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, and all other input signals are ?don?t care?. however, power-down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the dll-disabled power-down mode. the power-down state is synchronously exited when c ke is registered high (al ong with a nop or deselect command). a valid, executable command may be applied one clock cycle later. figure 30 power down t is t is ck ck cke command no column access in progress valid nop valid don?t care exit power down mode enter power down mode (burst read or write operation must not be in progress) nop
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 46 rev. 1.06, 2004-01 09192003-lfq1-r60g note: 1. cken is the logic state of cke at clock edge n: cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences no t shown are illegal or reserved table 7 truth table 2: clock enable (cke) current state cke n-1 cken command n action n notes previous cycle current cycle self refresh l l x main tain self-refresh ? self refresh l h deselect or nop exit self-refresh 1) power down l l x maintain power-down ? power down l h deselect or nop exit power-down ? all banks idle h l deselect or no pprecharge powe r-down entry ? all banks idle h l auto refresh self refresh entry ? bank(s) active h l deselect or nop active power-down entry ? hhsee ?truth table 3: current state bank n - command to bank n (same bank)? on page 47 ?? 1) deselect or nop commands should be issued on any clock edges occurring during the self refresh exit ( t xsnr ) period. a minimum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 47 rev. 1.06, 2004-01 09192003-lfq1-r60g . table 8 truth table 3: current state bank n - command to bank n (same bank) current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation 1) to 6) 1) this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). l h h h no operation nop. continue previous operation 1) to 6) 2) 2) this table is bank-specific, except wher e noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. idle l l h h active select and activate row 1) to 6) 3) 3) current state definitions: idle:t he bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with au to precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. l l l h auto refresh 1) to 7) 4) 4) the following states must not be interrupted by a command i ssued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the id le state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable comm ands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state& according to truth table 4. llllmode register set 1) to 7) 5) 5) the following states must not be inte rrupted by any executable command; desele ct or nop commands must be applied on each positive clock edge during these states. refreshing : starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all ban ks idle? state. accessing mode register: starts with registration of a mode register set command and ends when tmrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registrati on of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. row active l h l h read select co lumn and start read burst 1) to 6), 10) 6) all states and sequences not shown are illegal or reserved. l h l l write select column and start write burst 1) to 6), 10) 7) 7) not bank-specific; requires that all banks are idle. l l h l precharge deactivate row in bank(s) 1) to 6), 8) 8) may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. read (auto precharge disabled) l h l h read select column and start new read burst 1) to 6), 10) 9) 9) not bank-specific; burst termin ate affects the most recent r ead burst, regardless of bank. l l h l precharge truncate read burst, start precharge 1) to 6), 8) 10) 10) reads or writes listed in the comm and/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. l h h l burst terminate burst terminate 1) to 6), 9) 11) write (auto precharge disabled) l h l h read select column and start read burst 1) to 6), 10), 11) l h l l write select column and start write burst 1) to 6), 10) l l h l precharge truncate write burst, start precharge 1) to 6), 8), 11)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 48 rev. 1.06, 2004-01 09192003-lfq1-r60g 11) requires appropriate dm masking. table 9 truth table 4: current state bank n - command to bank m (different bank) current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation. 1) to 6) 2)3)4)5)6) l h h h no operation nop. continue previous operation. 1) to 6) idle xxxxany command otherwise allowed to bank m ? 1) to 6) row activating, active, or precharging l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7) l h l l write select column and start write burst 1) to 7) l l h l precharge ? 1) to 6) read (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7) l l h l precharge ? 1) to 6) write (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 8) l h l l write select column and start new write burst 1) to 7) l l h l precharge ? 1) to 6) read (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7), 10) 9) l h l l write select column and start write burst 1) to 7), 9), 10) l l h l precharge ? 1) to 6) write (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7), 9) l h l l write select column and start new write burst 1) to 7), 9) l l h l precharge ? 1) to 6) 1) this table applies when cke n-1 was high and cke n is high (see table 7 : clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table describes alternate bank operation, except wher e noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 49 rev. 1.06, 2004-01 09192003-lfq1-r60g 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see 10) . write with auto precharge enabled: see 10) . 4) auto refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank repr esented by the current state only. 6) all states and sequences not shown are illegal or reserved. 7) reads or writes listed in the command/action column incl ude reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8) requires appropriate dm masking. 9) concurrent auto precharge: this device supports ?concurrent auto precharge?. when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not inte rrupt the read or write data transfer and all other limitations apply (e.g. contention be tween read data and write data must be avoided). the minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 10 . 10) a write command may be applied after the completion of data output. table 10 truth table 5: concurrent auto precharge from command to command (different bank) minimum delay with concurrent auto precharge support unit write w/ap read or read w/ap 1 + (bl/2) + t wtr t ck write to write w/ap bl/2 t ck precharge or activate 1 t ck read w/ap read or read w/ap bl/2 t ck write or write w/ap cl (rounded up) + bl/2 t ck precharge or activate 1 t ck
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram functional description data sheet 50 rev. 1.06, 2004-01 09192003-lfq1-r60g 3.6 simplified state diagram figure 31 simplified state diagram self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a burst stop preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 51 rev. 1.06, 2004-01 09192003-lfq1-r60g 4 electrical characteristics 4.1 operating conditions attention: permanent damage to the device may occu r if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 11 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1?w? short circuit output current i out ?50?ma? table 12 input and output capacitances parameter symbol values unit note/ test condition min. typ. max. input capacitance: ck, ck c i1 -2.0 ? 3.0 pf 1) 1) these values are guarantee d by design and are tested on a sample base only. v ddq = v dd = 2.5 v 0.2 v, f = 100 mhz, t a = 25 c, v out(dc) = v ddq /2, v out (peak to peak) 0.2 v. unused pins are tied to ground. delta input capacitance ck, ck c di1 ??0.25pf 1) input capacitance: all other input-only pins c i2 2.0 ? 3.0 pf 1) delta input capacitance: all other input-only pins c di2 ??0.5pf 1)2) 2) dm inputs are grouped with i/o pins reflecting the fact that th ey are matched in loading to dq and dqs to facilitate trace matching at the board level. input/output capacitance: dq, dqs, dm c io 4.0 5.0 pf 1) delta input/output capacitance : dq, dqs, dm c dio ??0.5pf 1)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 52 rev. 1.06, 2004-01 09192003-lfq1-r60g table 13 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) 1) 0 c t a 70 c min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 2) 2) under all conditions, v ddq must be less than or equal to v dd . eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 3) 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 4) 4) v tt is not applied dire ctly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 7) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 7) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 7) input different ial voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 7)5) 5) v id is the magnitude of the difference between th e input level on ck and the input level on ck . vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 6) 6) the ratio of the pull-up current to the pull-down current is specified for the sa me temperature and volt age, over the entire temperature and voltage range, for device drain to source volt age from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 7)8) 7) inputs are not recognized as valid until v ref stabilizes. 8) values are shown per component output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 7) output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v 7) output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 7)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 53 rev. 1.06, 2004-01 09192003-lfq1-r60g 4.2 normal strength pull-down and pull-up characteristics 1. the nominal pulldown v-i curve fo r ddr sdram devices is expected, bu t not guaranteed, to lie within the inner bounding lines of the v-i curve. 2. the full variation in driver pulldown current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v-i curve. 3. the nominal pullup v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve. 4. the full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v-i curve. 5. the full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. the full variation in the ratio of the nominal pullup to pulldown current should be unity 10 % , for device drain to source voltages from 0.1 to 1.0 v. figure 32 normal strength pull-down characteristics figure 33 normal strength pull-up characteristics 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 120 140 1 out (ma) v ddq - v out (v) maximum nominal high nominal low minimum maximum nominal high nominal low minimum v ddq - v out (v) 0.5 1 1.5 2 2.5 0 0 -20 -40 -60 -80 -100 -120 -140 -160 i out (ma)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 54 rev. 1.06, 2004-01 09192003-lfq1-r60g table 14 normal strength pull-down and pull-up currents voltage (v) pulldown current (ma) pullup current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 table 15 pull-down and pull-up pr ocess variations and conditions parameter nominal minimum maximum operating temperature 25 c0 c70 c v dd / v ddq 2.5 v 2.3 v 2.7 v process corner typical slow-slow fast-fast
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 55 rev. 1.06, 2004-01 09192003-lfq1-r60g 4.3 weak strength pull-down and pull-up characteristics 1. the weak pulldown v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve 2. the weak pullup v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve. 3. the full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v-i curve. 4. the full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 5. the full variation in the ratio of the nominal pullup to pulldown current should be unity 10 % , for device drain to source voltages from 0.1 to 1.0v. figure 34 weak strength pull-down characteristics figure 35 weak strength pull-up characteristics 0 10 20 30 40 50 60 70 80 0,00,51,01,52,02,5 vout [v] iout [ma] maxim um typical high typical low minim um -80,0 -70,0 -60,0 -50,0 -40,0 -30,0 -20,0 -10,0 0,0 0,0 0,5 1,0 1,5 2,0 2,5 vout [v] iout [v] maximum typical high typical low minimum
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 56 rev. 1.06, 2004-01 09192003-lfq1-r60g table 16 weak strength driver pull-down and pull-up characteristics voltage (v) pulldown current (ma) pullup current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 57 rev. 1.06, 2004-01 09192003-lfq1-r60g 4.4 ac characteristics (notes 1-5 apply to the following tables; electrical c haracteristics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and elec trical characteristics and ac timing.) notes: 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specific ations and device operation are guaranteed for the full voltage range specified. 3. figure 36 represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers w ill correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5 v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use condit ions. the minimum slew rate for the input signals is 1 v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as define d in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level). 6. for system characteristics like setu p & holdtime derating for slew ra te, i/o delta rise/fall derating, ddr sdram slew rate standards, overshoot & undershoot specification and clamp v - i characteristics see the latest jedec specificat ion for ddr components. figure 36 ac output load circuit diagram / timing reference load 50 ? timing reference point output ( v out ) 30 pf v tt
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 58 rev. 1.06, 2004-01 09192003-lfq1-r60g table 17 ac operating conditions 1) parameter symbol values unit note/ test condition min. max. input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 ? v 2)3) input low (logic 0) voltage, dq, dqs and dm signals v il(ac) ? v ref - 0.31 v 2)3) input differential voltage, ck and ck inputs v id(ac) 0.7 v ddq + 0.6 v 2)3)4) input closing point voltage, ck and ck inputs v ix(ac) 0.5 v ddq - 0.2 0.5 v ddq + 0.2 v 2)3)5) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v 2) input slew rate = 1 v/ns. 3) inputs are not recognized as valid until v ref stabilizes. 4) v id is the magnitude of the difference between th e input level on ck and the input level on ck . 5) the value of v ix is expected to equal 0.5 v ddq of the transmitting device and must track variations in the dc level of the same. table 18 ac timing - absolute specifications ?8/?7/-6 parameter symbol ?8 ?7 ?6 note/ test conditi on 1) ddr200 ddr266a ddr333 min. max. min. max. min. max. dq output access time from ck/ck t ac ?0.8 +0.8 ?0.75 +0.75 ?0.7 +0.7 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.8 +0.8 ?0.75 +0.75 ?0.6 +0.6 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )min. ( t cl , t ch ) 2)3)4)5) clock cycle time t ck3 8 12 7 12 6 12 cl = 3.0 2)3)4)5) t ck2.5 8 12 7 12 6 12 cl = 2.5 2)3)4)5) t ck2 10 12 7.5 12 7.5 12 cl = 2.0 2)3)4)5) t ck1.5 10 12 ? ? 0.45 ? cl = 1.5 2)3)4)5) dq and dm input hold time t dh 0.6 ? 0.5 ? 0.45 ? 2)3)4)5) dq and dm input setup time t ds 0.6 ? 0.5 ? 2.2 ? 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.5 ? 2.2 ? 1.75 ? 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 2.0 ? 1.75 ? ?0.7 +0.7 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.8 +0.8 ?0.75 +0.75 ?0.7 +0.7 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.8 +0.8 ?0.75 +0.75 0.75 1.25 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 ? +0.40 2)3)4)5)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 59 rev. 1.06, 2004-01 09192003-lfq1-r60g dqs-dq skew (dqs and associated dq signals) t dqsq ?+0.6 ? +0.5 t hp ? t qhs ? 2)3)4)5) data hold skew factor t qhs ? 1.0 ? 0.75 0.2 ? 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?0.2? 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? 2 ? 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? 0 ? 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? 0.40 0.60 2)3)4)5) mode register set command cycle time t mrd 2 ? 2 ? 0.25 ? 2)3)4)5) write preamble setup time t wpres 0 ? 0 ? 0.75 ? 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 0.8 ? 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? 0.75 ? 2)3)4)5) address and control input setup time t is 1.1 ? 0.9 ? 0.8 ? fast slew rate 3)4)5)6)10) 1.1 ? 1.0 ? 0.9 1.1 slow slew rate 3)4)5)6)10) address and control input hold time t ih 1.1 ? 0.9 ? 0.40 0.60 fast slew rate 3)4)5)6)10) 1.1 ? 1.0 ? 42 70e+3 slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 60 ? cl > 1.5 2)3)4)5) t rpre1.5 0.9 1.1 na 72 ? cl = 1.5 2)3)4)5)11) read preamble setup time t rpres 1.5 ? na 18 ? 2)3)4)5)12) read postamble t rpst 0.40 0.60 0.40 0.60 18 ? 2)3)4)5) active to precharge command t ras 50 120e+3 45 120e+3 18 ? 2)3)4)5) active to active/auto-refresh command period t rc 70 ? 65 ? 12 ? 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 80 ? 75 ? 15 ? 2)3)4)5) active to read or write delay t rcd 20 ? 20 ? 2)3)4)5) precharge command period t rp 20 ? 20 ? 1 ? 2)3)4)5) active to autoprecharge delay t rap 20 ? 20 ? 75 ? 2)3)4)5) active bank a to active bank b command t rrd 15 ? 15 ? 200 ? 2)3)4)5) write recovery time t wr 15 ? 15 ? ? 7.8 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)13) table 18 ac timing - absolute specifications ?8/?7/-6 (cont?d) parameter symbol ?8 ?7 ?6 note/ test conditi on 1) ddr200 ddr266a ddr333 min. max. min. max. min. max.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 60 rev. 1.06, 2004-01 09192003-lfq1-r60g internal write to read command delay t wtr 1? 1 ? t ck cl > 1.5 2)3)4)5) t wtr1.5 2? ?? t ck cl = 1.5 2)3)4)5) exit self-refresh to non-read command t xsnr 80 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ?7.8 ? 7.8 s 2)3)4)5)14) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v 2) input slew rate 1 v/ns for ddr400, ddr333, ddr266, and = 1 v/ns for ddr200 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timi ng reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee devi ce timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a vali d transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a pr evious write was in progress, dqs could be high, low, or transitioning fr om high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. th e device operates with a greater value for this parameter, but system performance (bus turnar ound) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v oh(ac) and v ol(ac) . 11) cas latency 1.5 operation is supported on ddr200 devices only 12) t rpres is defined for cl = 1.5 operation only 13) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 14) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. table 18 ac timing - absolute specifications ?8/?7/-6 (cont?d) parameter symbol ?8 ?7 ?6 note/ test conditi on 1) ddr200 ddr266a ddr333 min. max. min. max. min. max.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 61 rev. 1.06, 2004-01 09192003-lfq1-r60g table 19 ac timing for ddr266(a) - applicable specs in clock cycles parameter symbol ddr266(a) @cl = 2 units notes 1) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v min. max. mode register set command cycle time t mrd 2? t ck 2)3)4)5)6) 2) input slew rate = 1 v/ns. 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) t hz and t lz transitions occur in the same acce ss time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). write preamble t wpre 0.25 ? t ck 2) to 6) active to precharge command t ras 6 16000 t ck 2) to 6) active to active/auto-refresh command period t rc 9? t ck ddr266a 2) to 6) 8? t ck ddr266 2) to 6) auto-refresh to active/auto-refresh command period t rfc 10 ? t ck 2) to 6) active to read or write delay t rcd 3? t ck ddr266a 2) to 6) 2? t ck ddr266 2) to 6) precharge command period t rp 3? t ck ddr266a 2) to 6) 2? t ck ddr266 2) to 6) active bank a to active bank b command t rrd 2? t ck 2) to 6) write recovery time t wr 2? t ck 2) to 6) auto precharge write recovery + precharge time t dal 5? t ck 2) to 6) internal write to read command delay t wtr 1? t ck 2) to 6) exit self-refresh to non-read command t xsnr 17 ? t ck 2) to 6) exit self-refresh to read command t xsrd 200 ? t ck 2) to 6)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 62 rev. 1.06, 2004-01 09192003-lfq1-r60g table 20 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs chan ging once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; powe r-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 63 rev. 1.06, 2004-01 09192003-lfq1-r60g table 21 i dd specification and conditions part number & organization ddr200 ddr266 ddr333 unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition for typical values: v dd =2.5v, t a = 25 c, test conditions for maximum values: v dd =2.7v, t a =10c symbol typ. max. typ.. max. typ. max. i dd0 65 85 72 90 82 105 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 67 100 74 110 84 125 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 2.4 4.5 2.7 5.0 3.0 5.5 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 17 35 22 45 25 58 ma 5) i dd2q 12 35 16 45 19 58 ma 5) i dd3p 12 15 12 15 12 15 ma 5) i dd3n 25 35 32 45 38 58 ma 5) i dd4r 54 90 69 110 83 120 ma 3)4) i dd4w 65 95 84 110 102 130 ma 3) i dd5 142 180 153 190 161 205 ma 3) i dd6 standard version 1.9 2.5 1.9 2.5 1.9 2.5 ma 5) low power version 0.9 1.0 0.9 1.0 0.9 1.0 ma i dd7 2160 2240 2430 2520 2440 2600 ma 4)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram electrical characteristics data sheet 64 rev. 1.06, 2004-01 09192003-lfq1-r60g 4.4.1 i dd current measurement conditions i dd1 : operating current: one bank operation 1. only one bank is accessed with t rc (min) , burst mode, address and control inputs on nop edge are changing once per clock cycle. i out =0 ma. 2. timing patterns 3. ddr200 (100 mhz, cl = 2): t ck =10ns, cl=2, bl=4, t rcd =2 t ck , t ras =5 t ck setup: a0 n r0 n n p0 n read : a0 n r0 n n p0 n - repeat the same timing with random address changing 50% of data changing at every burst changing at every burst 4. ddr266 (133 mhz, cl = 2): t ck = 7.5 ns, cl = 2, bl = 4, t rcd =3 t ck , t rc =9 t ck , t ras =5 t ck setup: a0 n n r0 n p0 n n n read : a0 n n r0 n p0 n nn - repeat the same timing with random address changing 50% of data changing at every burst 5. ddr333 (166 mhz, cl = 2.5): t ck = 6 ns, cl = 2.5, bl = 4, t rcd =3 t ck , t rc =9 t ck , t ras =5 t ck setup: a0 n n r0 n p0 n n n read : a0 n n r0 n p0 n n n - repeat the same timing with random address changing 50% of data changing at every burst 6. legend: a = activate, r = read, w = write, p = precharge, n = nop i dd7 : operating current: four bank operation 1. four banks are being interleaved with t rcmin . burst mode, address and control inputs on nop edge are not changing. i out =0 ma. 2. timing patterns a) ddr200 (100 mhz, cl = 2): t ck =10ns, cl=2, bl=4, t rrd =2 t ck , t rcd =3 t ck , read with autoprecharge setup: a0 n a1 r0 a2 r1 a3 r2 read: a0 r3 a1 r0 a2 r1 a3 r2 - repeat the same timing with random address changing 50% of data changing at every burst b) ddr266a (133 mhz, cl = 2): t ck = 7.5 ns, cl = 2, bl = 4, t rrd =2 t ck , t rcd =3 t ck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read: a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every burst c) ddr333 (166 mhz, cl = 2.5): t ck = 6 ns, cl = 2.5, bl = 4, t rrd =2 t ck , t rcd =3 t ck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read: a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every burst 3. legend: a = activate, r = read, w = write, p = precharge, n = nop
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 65 rev. 1.06, 2004-01 09192003-lfq1-r60g 5 timing diagrams figure 37 data input (write), timing burst length = 4 figure 38 data output (read), timing burst length = 4 t dh t ds t dh t ds t dqsl di n = data in for column n. 3 subsequent elements of data in are applied in programmed order following di n. di n dqs dq dm don?t care t dqsh t qh (data output hold time from dqs) t dqsq and t qh are only shown once and are shown referenced to differe nt edges of dqs, only for clarify of illustration. . dqs dq t dqsq max t qh t dqsq and t qh both apply to each of the four relevant edges of dqs. t dqsq max. is used to determine the worst case setup time for controller data capture. t qh is used to determine the worst case hold time for controller data capture.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 66 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 39 initialize and mode register sets t ih 200 s t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t mrd t rfc t rfc t rp t mrd t mrd t cl t ck t ch t vtd initialize and mode register sets pre emrs mrs pre ar ar mrs nop act code code code ra code code code ra ba0=l ba0=l ba high-z high-z power-up: vdd and ck stable extended mode register set load mode register, reset dll load mode register (with a8 = l) vdd vddq vtt (system * ) vref ck cke command dm a0-a9, a11 a10 ba0, ba1 dqs dq lvcmos low level all banks ba0=h ba1=l ba1=l ba1=l all banks * vtt is not applied directly to the device, however t vtd must be ** t mrd is required before any command can be applied and the two autorefresh commands may be moved to follow the first mrs, greater than or equal to zero to avoid device latchup. 200 cycles of ck are required before a read command can be applied. but precede the second precharge all command. don?t care 200 cycles of ck ** ck
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 67 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 40 power down mode t ih t is t ih t is t is t is t ih t is t cl t ch t ck nop valid valid * valid valid enter power down mode exit power down mode no column accesses are allowed to be in progress at the time power down is entered. * = if this command is a precharge (or if the device is already in the idle state) then the power down mode shown is precharge power down. if this command is an active (or if at least one row is already active), then the power down mode shown is active power down. cke command addr dqs dq dm don?t care c k c k nop
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 68 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 41 auto refresh mode t ih t is t ih t is t ih t is t rfc t rp t cl t ch t ck pre nop nop ar nop ar nop nop nop ra ra ba pre = precharge; act = active; ra = row address; ba = bank address; ar = autorefresh. nop commands are shown for ease of illustration; ot her valid commands may be possible at these times. dm, dq, and dqs signals are all don't care/high-z for operations shown. valid valid act ra cke command a0-a8 a9, a11-a13 a10 ba0, ba1 dqs dq dm bank(s) don?t care all banks one bank t rfc ck ck
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 69 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 42 self refresh mode 200 cycles t ih t is t xsrd, t xsrn t ih t is t is t is t ih t is t rp * t ck t cl t ch ar valid nop valid enter self refresh mode exit self refresh mode nop * = device must be in the all banks idle state before entering self refresh mode. ** = t xsnr is required before any non-r ead command can be applied, and t xsrd (200 cycles of ck). cke command addr dqs dq dm don?t care are required before a read command can be applied. ck ck clock must be stable before exiting self refresh mode
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 70 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 43 read without auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck pre nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration ; other commands may be valid at these times. ba x ba x valid valid valid nop read col n ra ra ba x * do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 all banks one bank t dqsck (max) t rpre cl=1.5 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n c k c k dis ap dis ap = disable auto precharge. t rpres
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 71 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 44 read with auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck read without auto precharge (cas latency = 2, burst length = 4) pre nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x ba x valid valid valid nop read col n ra ra ba x * do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 all banks one bank t dqsck (max) t rpre cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n c k c k dis ap dis ap = disable auto precharge.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 72 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 45 bank read access (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck read without auto precharge (cas latency = 2, burst length = 4) nop nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. en ap = enable auto precharge. act = active; ra = row address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x valid valid valid nop read col n ra ra do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 t dqsck (max) t rpre cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n en ap ba x c k c k t lz (min)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 73 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 46 write without auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck read without auto precharge (cas latency = 2, burst length = 4) read nop pre nop nop act nop nop ba x ba x* valid nop act ra ra ba x do n c k c k cke command a10 ba0, ba1 dm dqs dq dqs dq t dqsck (max) t rpre cl=2 cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n col n ra ra all banks ra one bank dis ap ba x t rp do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. t rcd a0-a9, a11, a12 t ras t rc t lz (min)
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 74 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 47 write with auto precharge (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t rp t cl t ch t ck write without auto precharge (burst length = 4) nop nop nop pre nop nop act nop ba x ba nop write col n ra ra ba x * valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. din c k c k cke command a10 ba0, ba1 dqs dq dm dis ap all banks one bank t wr t wpres t dqsh don?t care a0-a9, a11, a12 t dqss = min. t dqss t wpre t dsh
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 75 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 48 bank write access (burst length = 4) nop commands are shown for ease of illustration; othe r valid commands may be possible at these times. act = active; ra = row address; ba = bank address. t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t is t rp t cl t ch t ck write without auto precharge (burst length = 4) nop nop nop nop nop nop act nop ba x ba nop write col n ra ra valid din = data in for column n. 3 subsequent elements of data in are app lied in the programmed order following din. en ap = enable auto precharge. c k c k cke command a10 ba0, ba1 dqs dq dm t wr t dqss t wpres t dqsh don?t care valid valid en ap a0-a9, a11, a12 t dal t dqss = min. t dsh t wpre din
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 76 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 49 write dm operation (burst length = 4) t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck t ras bank write access (burst length = 4) write nop nop nop nop pre nop nop ba x nop act ra ra di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. din valid ba x cke command a10 ba0, ba1 dqs dq dm ck ck t wpres t wr t rcd all banks one bank dis ap don?t care a0-a9, a11, a12 col n ba x t dqss t dqsh t dsh t wpre t dqss = min.
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram timing diagrams data sheet 77 rev. 1.06, 2004-01 09192003-lfq1-r60g figure 50 write dm operation (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop pre nop nop act nop nop write col n ra din ck ck cke command a10 ba0, ba1 dqs dq dm t wr t dqss don?t care valid t ih t is t ih t is ba x ba ra ba x * all banks one bank dis ap di n = data in for column n. 3 subsequent elements of data in are applied in the programmed or der following di n (the second element of the 4 is masked). dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. a 0-a9, a11, a12 t dqsh t dsh t dqss = min. t wpres
hyb25d128[400/800/160]a-[6/7/8] 128mbit double data rate sdram package outlines data sheet 78 rev. 1.06, 2004-01 09192003-lfq1-r60g 6 package outlines figure 51 thin small outline package p-tsopii-66 (hyb25d128[400/800/160]a-[6/7/8]) tsop66 0,65 basic 0,3 0,08 0,805 ref 0,05 min 1,20 max 22,220,13 lead #1 10,160,13 0,50,1 11,760,2 0.1 0,25 basic gauge plane seating plane
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